`timescale 1ns/1ns
module test;

   reg rst;
   reg clk;
   wire [7:0] count;

   initial
     begin
	   rst = 1; 
	   clk = 0;
	   #20 rst = 0;
     end
   
   always #5 clk = ~clk;
        
   counter #(
	     .WIDTH(8)
	     ) mycounter (
			  .rst(rst),
			  .clk(clk),
			  .count(count));
endmodule // test

